Predicting CMOS Speed with Gate Oxide and Voltage Scaling and Interconnect Loading Effects
نویسندگان
چکیده
Sub-quarter micron MOSFET’s and ring oscillators with 2.5–6 nm physical gate oxide thicknesses have been studied at supply voltages of 1.5–3.3 V. Idsat can be accurately predicted from a universal mobility model and a current model considering velocity saturation and parasitic series resistance. Gate delay and the optimal gate oxide thickness were modeled and predicted. Optimal gate oxide thicknesses for different interconnect loading are highlighted.
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